Introduction: Whether you are a logic designer, hardware engineer or system engineer, or even have all these titles, as long as you use FPGA in any kind of high-speed and multi-protocol complex system, you will probably need to work hard to solve the device. Configuration, power management, IP integration, signal integrity and other key design issues.
However, you don’t have to face these challenges alone, because the application engineers working in the current industry’s leading FPGA companies face these problems every day, and they have put forward some design guidelines and guidelines that will make your design work easier. solution. Master the three golden rules of FPGA design to make your design easier.
1. The principle of balance exchange between area and speed
The area here refers to the chip resources of the FPGA, including logic resources and I/O resources, etc.; the speed here refers to the highest frequency of FPGA work (unlike DSP or ARM, the working frequency of FPGA design is not fixed, and It is closely related to the delay of the design itself). In actual design, using the smallest area to design the highest speed is the goal pursued by every developer, but "fish and bear's paw can't have both", the choice between shows the wisdom of a developer.
1. Speed change area
The speed advantage can be exchanged for area savings. The smaller the area, it means that the function of the product can be realized at a lower cost. The principle of speed for area is often used in some more complex algorithm designs. In these algorithm designs, pipeline design is often a technology that must be used. In the design of the pipeline, these modules that are reused but used at different times will take up a lot of FPGA resources. The design technology of FPGA is modified to extract the smallest multiplexing unit from the algorithm modules that are reused, and use this smallest high speed to replace the modules that are reused but different times in the original design. Of course, in the process of transformation, some other resources will inevitably be added to realize this replacement process. But as long as the speed has advantages, the added part of the logic can still achieve the purpose of reducing the area and increasing the speed.
It can be seen that the key to speed change area is the multiplexing of high-speed basic units.
2. Area change speed
In this method, area replication can be exchanged for an increase in speed. The higher the supported speed, it means that higher product performance can be achieved. Some application fields that focus on product performance can use parallel processing technology to achieve area conversion speed.
2. Hardware achievable principle
FPGA design usually uses HDL language, such as Verilog HDL or VHDL. When using HDL language to describe the function of a hardware circuit, you must ensure that the circuit described by the code is hardware achievable.
The syntax of Verilog HDL language is very similar to C language, but there are essential differences between them. C language is a high-level language based on procedures, which can be run on the CPU after compilation. The Verilog HDL language describes itself as a hardware structure, and it is a hardware circuit after compilation. Therefore, some statements are not problematic in the C language environment, but in the HDL language environment, the results will be incorrect or unsatisfactory. Such as:
for(i=0;i<16;i++)
DoSomething();
There is no problem in running in C language, but compiling in the environment of Verilog HDL will result in a serious waste of resources after synthesis.
3. Synchronous design principles
Synchronous circuit and asynchronous circuit are two basic circuit structures designed by FPGA.
The biggest disadvantage of asynchronous circuits is that they produce glitches. The core circuit of synchronous design is composed of various flip-flops. Any output of this type of circuit is generated by driving a flip-flop on the edge of a certain clock. Therefore, the synchronous design can well avoid the generation of burrs.
